Sponsors: SRC, ONR, NSF, Intel, AMD

As the silicon transistor is scaled to deep submicrometer gate lengths, the microprocessor thermal management challenge has been extended to nanoscale thermal conduction and coupled electron-phonon transport within and near the active regions of devices. The electron temperatures in modern silicon devices can exceed several thousand Kelvin, which results in severe nonequilibrium between generated phonons and those responsible for conduction cooling of devices. These problems are amplified in novel transistor geometries (including silicon-on-insulator, FINFET, and related nanopillar devices) which impair heat conduction between active regions and the substrate.

Stanford has been at the forefront of electrothermal transport modeling and experiments for silicon nanotransistors for nearly two decades. Early work focused on thermal property measurements for silicon devices, including SOI silicon nanolayer and oxide layer conductivities. A variety of device thermometry techniques were developed, including gate electrical-resistance techniques (for DC temperature rise) and laser-reflectance thermometry (for 10 ns temporal resolution). More recently, our work has focused on the sub-continuum and nonequilibrium electron and phonon transport within active regions. This included solutions to the phonon Boltzmann transport equation both in SOI transistors and in traditional bulk devices, followed by coupled Monte Carlo/BTE simulations of both the electron and phonon systems in parallel. The goals of this research have been predictions of the impact on channel mobility, interconnect MTF, and device leakage currents.