Sponsors: Intel, SRC, MARCO IFC, Texas Instruments
With the scaling of silicon nanotransistors into the deep submicrometer regime, a variety of compounding factors are increasing the temperature rise in the multilevel interconnect systems in modern VLSI circuits. These include increasing levels of metallization layers, which increase the thermal resistance to the high conductivity substrate, as well as higher current densities and the exploration of novel dielectric materials with relatively low thermal conductivities.
Stanford has made extensive contributions to the measurement of thermal conduction properties relevant for multilevel interconnects, as well as the prediction of temperature distributions and the measurement of temperature distributions along interconnects. Thermal conductivity measurements using both pattern electrical bridges and laser-reflectance techniques yielded data for conventional silicon oxides as a function of processing conditions as well as for novel organic passivation candidate materials. Nanosecond scanning laser-reflectance thermometry determined the temperature distributions along interconnects during rapid heating events such as those incurred during electrostatic discharge events. Simulations determined the scaling of temperature distributions with decreasing channel dimensions as well as the impact of current concentration in multilevel via structures.