Chirag & Joe led a novel heat sink design for GaN power electronics and co-authored the best poster at the Applied Power Electronics Conf. in San Antonio TX
Here is the full reference for the poster, which is collaborative with the Pilawa group at UIUC: N. Pallo, C. Kharangate, T. Modeer, J. Schaadt, M. Asheghi, K. Goodson, R.C.N. Pilawa-Podgurski, “Modular Heat Sink for Chip-Scale GaN Transistors in Multilevel Converters”, IEEE Applied Power Electronics Conference, San Antonio, Texas, 2018.
This is supported by the NSF POETs center, and the awards are quite competitive. Well done Chirag and Joe!