Won, Y., Cho, J., Agonafer, D., Asheghi, M., Goodson, K.E., 2015, “Fundamental Cooling Limits for High Power Density GaN Electronics,” IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 5, pp. 737-744.



The peak power density of GaN high-electron-mobility transistor technology is limited by a hierarchy of thermal resistances from the junction to the ambient. Here, we explore the ultimate or fundamental cooling limits for junction-to fluid cooling, which are enabled by advanced thermal management technologies, including GaN–diamond composites and nanoengineered heat sinks. Through continued attention to near-junction resistances and extreme flux convection heat sinks, heat fluxes beyond 300 kW/cm2 from individual 2-μm gates and 10 kW/cm2 from the transistor footprint will be feasible. The cooling technologies under discussion here are also applicable to thermal management of 2.5-D and 3-D logic circuits at lower heat fluxes.