Sponsors: Google
Thermal-power challenges and increasingly expensive energy demands pose threats to the historical rate of increase in processor performance. Energy-efficient computing schemes and heterogeneous integration (including but not limited to 2.5 & 3D chips) promise substantial reduction in energy demand for emerging and growing computing needs. However, these conflicting trends have resulted in a substantial increase in both heat flux and power density (W/cm3), which makes it even more challenging to use conventional cooling technology solutions.
We are working collaboratively with Google to explore the extreme limits of power density for these high heat flux chips with an emphasis on server applications. Recently, Stanford demonstrated heat dissipation levels ~ 250 W/cm2 at ~60 oC and 800 W/cm2 at ~160oC using single-phase water (inlet temperature~25oC) as well as 700 W/cm2 @ 130oC superheat using two-phase boiling R245fa at ~25oC inlet temperature by developing a silicon-based embedded microchannel and a specialized 3D manifold µ-cooler with (52 mm2 foot print). We will leverage the existing R&D research and infrastructure at Stanford to explore the limits of cooling for high heat flux application for this project.
Stanford is exploring the limits of high heat flux cooling ~ 1000 W/cm2 using single phase water and single/two-phase R245fa on a 52 mm2 microprocessor foot print, this is for rapid turn around and optimization using existing thermal test vehicles (TTVs) at Stanford. This is justified since the embedded microchannels with 3D-manifold µ-cooler basically scale with the area. We will also consider single-phase CFD simulations for larger microprocessor foot prints of 102 mm2 and 252 mm2 to help with design, optimization and microfabrication of large area TTVs.
We are also exploring the performance metrics and feasibility of a novel and breakthrough Extreme Heat Flux µ-cooler (EHFM) device capable of removing extreme heat flux levels of 1,500 W/cm2 at a temperature superheat <10 oC, resulting in a thermal resistance, Rth < 0.01 oC/W over large areas of 102 mm2 and COP ~ 10,000. The concept EHFM device, see Figure 3, utilizes a liquid wicking and thin-film evaporation from an electroplated copper inverse opal (CIO) porous structure [7,8] along with a 3-D manifold with liquid routing and vapor extraction conduits. The proposed concept device reduces the peak junction temperature, while increasing the reliability and packaging density, in microprocessors and power electronics. The proposed performance metric represents 10× and 100× reduction in thermal resistance and COP, respectively, over the state-of-art cooling technologies.
