Effect of Microscale Thermal Conduction on the Packing Limit of Silicon-on-Insulator Electronic Devices

Goodson, K.E., and Flik, M.I., 1992, "Effect of Microscale Thermal Conduction on the Packing Limit of Silicon-on-Insulator Electronic Devices," IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 15, pp. 715-722.

Download PDF

Silicon-on-insulator (SOI) electronic circuits have a buried silicon dioxide layer which inhibits device cooling and reduces the thermal packing limit, the largest number of devices per unit substrate area for which the device operating temperature is acceptably low. Thermal analysis yields the packing limit of SOI MOSFET devices in terms of the targeted channel-to-substrate thermal conductance. Thermal conduction is microscale if it is significantly reduced by the boundary scattering of heat carriers, phonons in silicon and electrons in aluminum. Microscale effects are negligible above room temperature, but may reduce the packing limit by 44 % for a substrate temperature of 77 K.

Related Projects

As the silicon transistor is scaled to deep submicrometer gate lengths, the microprocessor thermal management challenge has been extended to nanoscale thermal conduction and coupled electron-phonon...
The basic physics of phonon conduction in dielectrics and semiconductors has been the focus of research for more than a century. However, recent improvements in nanofabrication technologies have...